Virtual AC cycling within an information handling system

ABSTRACT

A method and an information handling system (IHS) provides a virtual alternating current (vAC) reset of the IHS. A vAC reset module (vACRM), in response to receiving a request for the vAC reset, sets a bit within an auxiliary (AUX) based register to invoke the vAC reset when a system restart command is issued. The vACRM changes/configures a vAC recovery policy to enable main rail power to be turned on and a system start-up procedure to be initiated when a restored vAC is detected. The vACRM uses a system restart command to shutdown the main rail power and to remove power from system components powered by the main rail. The vACRM switches off AUX power to AUX powered components, based on the previously set bit, and reapplies the AUX power, following a preset interval. The vACRM turns on main rail power and initiates a system start-up procedure, according to the vAC recovery policy.

BACKGROUND 1. Technical Field

The present disclosure generally relates to information handling systems(IHS) and in particular to auxiliary power cycling within informationhandling systems.

2. Description of the Related Art

As the value and use of information continue to increase, individualsand businesses seek additional ways to process and store information.One option available to users is information handling systems. Aninformation handling system (IHS) generally processes, compiles, stores,and/or communicates information or data for business, personal, or otherpurposes, thereby allowing users to take advantage of the value of theinformation. Because technology and information handling needs andrequirements vary between different users or applications, informationhandling systems may also vary regarding what information is handled,how the information is handled, how much information is processed,stored, or communicated, and how quickly and efficiently the informationmay be processed, stored, or communicated. The variations in informationhandling systems allow for information handling systems to be general orconfigured for a specific user or specific use such as financialtransaction processing, airline reservations, enterprise data storage,or global communications. In addition, information handling systems mayinclude a variety of hardware and software components that may beconfigured to process, store, and communicate information and mayinclude one or more computer systems, data storage systems, andnetworking systems.

As information handling systems increase in complexity, rich featuresets provide greater manageability, serviceability, and expandability.In numerous cases, this increased complexity has also resulted inincreasing amount of critical logic being run on flea power/Aux powerdomain. This complexity opens more extreme remote corner cases forserver system failures.

Traditionally, data center managers/administrators have been utilizingan external alternating current (AC) cycle method as a last resort torecover failed server systems. Although the AC cycle method is primarilyemployed as a last resort, an AC cycle has become a critical tool introubleshooting. The AC cycle method requires an onsite technician toremove and reconnect an AC power cord or a smart-switched powerdistribution unit (PDU) connected to a network to AC cycle the serversystem remotely. However, smart-switched PDUs are expensive. As aresult, a large percentage of a server install base does not deployswitched PDUs. Instead of using the switched PDU, other traditionalapproaches involve providing a manual AC cycle in which a localtechnician is deployed to physically remove and subsequently replace anAC power cord. For the manual AC cycle, the local technician presentsadditional overhead to operating a datacenter.

BRIEF SUMMARY

Disclosed are a method and an information handling system (IHS) thatprovides a virtual alternating current (vAC) reset of the IHS. A vACreset module (vACRM), in response to receiving a request for the vACreset, sets a bit within an auxiliary (AUX) based register to invoke thevAC reset when a system restart command is issued. The vACRMchanges/configures a vAC recovery policy to enable main rail power to beturned on and a system start-up procedure to be initiated when arestored vAC is detected. The vACRM uses a system restart command toshutdown the main rail power and to remove power from system componentspowered by the main rail. The vACRM switches off AUX power to AUXpowered components, based on the previously set bit, and reapplies theAUX power, following a preset interval. The vACRM turns on main railpower and initiates a system start-up procedure, according to the vACrecovery policy.

The above summary contains simplifications, generalizations andomissions of detail and is not intended as a comprehensive descriptionof the claimed subject matter but, rather, is intended to provide abrief overview of some of the functionality associated therewith. Othersystems, methods, functionality, features and advantages of the claimedsubject matter will be or will become apparent to one with skill in theart upon examination of the following figures and detailed writtendescription.

BRIEF DESCRIPTION OF THE DRAWINGS

The description of the illustrative embodiments can be read inconjunction with the accompanying figures. It will be appreciated thatfor simplicity and clarity of illustration, elements illustrated in thefigures have not necessarily been drawn to scale. For example, thedimensions of some of the elements are exaggerated relative to otherelements. Embodiments incorporating teachings of the present disclosureare shown and described with respect to the figures presented herein, inwhich:

FIG. 1 illustrates an example information handling system (IHS) withinwhich various aspects of the disclosure can be implemented, according toone or more embodiments;

FIG. 2 depicts a block diagram illustration of a data center environment(DCE) having a number of servers for which alternating current (AC)cycling can be performed, according to one or more embodiments;

FIG. 3 is a block diagram illustration of an example server platformhaving an auxiliary power switch, according to one or more embodiments;

FIG. 4 is a flow chart illustrating a method for performing a virtual ACreset via an in-band management connection, according to one embodiment;and

FIG. 5 is a flow chart illustrating a method for performing a virtual ACreset via an out-of-band management connection, according to oneembodiment.

DETAILED DESCRIPTION

The illustrative embodiments provide a method and an informationhandling system (IHS) that provides a virtual alternating current (vAC)reset of the IHS. A vAC reset module (vACRM), in response to receiving arequest for the vAC reset, sets a bit within an auxiliary (AUX) basedregister to invoke the vAC reset when a system restart command isissued. The vACRM changes/configures a vAC recovery policy to enablemain rail power to be turned on and a system start-up procedure to beinitiated when a restored vAC is detected. The vACRM uses a systemrestart command to shutdown the main rail power and to remove power fromsystem components powered by the main rail. The vACRM switches off AUXpower to AUX powered components, based on the previously set bit, andreapplies the AUX power, following a preset interval. The vACRM turns onmain rail power and initiates a system start-up procedure, according tothe vAC recovery policy.

As described herein, the term “virtual alternating current (vAC) reset”refers to operations that includes removing and restoring power tosystem logic (i.e., Main and AUX components/logic) in order to provide aremote vAC cycle of all of the server components. The vAC is performedwithout requiring an external smart-switched power distribution unit(PDU) and without requiring manual AC cord removal and reinsertion by adata center technician.

In the following detailed description of exemplary embodiments of thedisclosure, specific exemplary embodiments in which the disclosure maybe practiced are described in sufficient detail to enable those skilledin the art to practice the disclosed embodiments. For example, specificdetails such as specific method orders, structures, elements, andconnections have been presented herein. However, it is to be understoodthat the specific details presented need not be utilized to practiceembodiments of the present disclosure. It is also to be understood thatother embodiments may be utilized and that logical, architectural,programmatic, mechanical, electrical and other changes may be madewithout departing from general scope of the disclosure. The followingdetailed description is, therefore, not to be taken in a limiting sense,and the scope of the present disclosure is defined by the appendedclaims and equivalents thereof.

References within the specification to “one embodiment,” “anembodiment,” “embodiments”, or “one or more embodiments” are intended toindicate that a particular feature, structure, or characteristicdescribed in connection with the embodiment is included in at least oneembodiment of the present disclosure. The appearance of such phrases invarious places within the specification are not necessarily allreferring to the same embodiment, nor are separate or alternativeembodiments mutually exclusive of other embodiments. Further, variousfeatures are described which may be exhibited by some embodiments andnot by others. Similarly, various requirements are described which maybe requirements for some embodiments but not other embodiments.

It is understood that the use of specific component, device and/orparameter names and/or corresponding acronyms thereof, such as those ofthe executing utility, logic, and/or firmware described herein, are forexample only and not meant to imply any limitations on the describedembodiments. The embodiments may thus be described with differentnomenclature and/or terminology utilized to describe the components,devices, parameters, methods and/or functions herein, withoutlimitation. References to any specific protocol or proprietary name indescribing one or more elements, features or concepts of the embodimentsare provided solely as examples of one implementation, and suchreferences do not limit the extension of the claimed embodiments toembodiments in which different element, feature, protocol, or conceptnames are utilized. Thus, each term utilized herein is to be given itsbroadest interpretation given the context in which that term isutilized.

Those of ordinary skill in the art will appreciate that the hardware,firmware/software utility, and software components and basicconfiguration thereof depicted in the following figures may vary. Forexample, the illustrative components of the IHS are not intended to beexhaustive, but rather are representative to highlight some of thecomponents that are utilized to implement certain of the describedembodiments. For example, different configurations of an IHS may beprovided, containing other devices/components, which may be used inaddition to, or in place of, the hardware depicted, and may bedifferently configured. The depicted example is not meant to implyarchitectural or other limitations with respect to the presentlydescribed embodiments and/or the general invention.

FIG. 1 illustrates a block diagram representation of an exampleinformation handling system (IHS) 100, within which one or more of thedescribed features of the various embodiments of the disclosure can beimplemented. For purposes of this disclosure, an information handlingsystem, such as IHS 100, may include any instrumentality or aggregate ofinstrumentalities operable to compute, classify, process, transmit,receive, retrieve, originate, switch, store, display, manifest, detect,record, reproduce, handle, or utilize any form of information,intelligence, or data for business, scientific, control, or otherpurposes. For example, an information handling system may be a handhelddevice, personal computer, a server, a network storage device, or anyother suitable device and may vary in size, shape, performance,functionality, and price. The information handling system may includerandom access memory (RAM), one or more processing resources such as acentral processing unit (CPU) or hardware or software control logic,ROM, and/or other types of nonvolatile memory. Additional components ofthe information handling system may include one or more disk drives, oneor more network ports for communicating with external devices as well asvarious input and output (I/O) devices, such as a keyboard, a mouse, anda video display. The information handling system may also include one ormore buses operable to transmit communications between the varioushardware components.

Referring specifically to FIG. 1, example IHS 100 includes one or moreprocessor(s) 102 coupled to system memory 106 via system interconnect104. System interconnect 104 can be interchangeably referred to as asystem bus, in one or more embodiments. Also coupled to systeminterconnect 104 is storage 134 within which can be stored one or moresoftware and/or firmware modules and/or data (not specifically shown).In one embodiment, storage 134 can be a hard drive or a solid statedrive. The one or more software and/or firmware modules within storage134 can be loaded into system memory 106 during operation of IHS 100. Asshown, system memory 106 can include therein a plurality of modules,including operating system (O/S) 108, Basic Input/Output System (BIOS)(110), application(s) 112 and firmware (not separately shown). In one ormore embodiments, BIOS 110 comprises additional functionality associatedwith unified extensible firmware interface (UEFI), and is thusillustrated as and can be more completely referred to as BIOS/UEFI 110in these embodiments. In addition, system memory 106 includes virtualalternating current reset module (vACRM) 114. The vACRM is also moresimply referred to herein as a reset management module (RMM). In one ormore embodiments, the vACRM/RMM is stored and/or executed within achassis power supply unit (e.g., PSU 304 of FIG. 3). The varioussoftware and/or firmware modules have varying functionality when theircorresponding program code is executed by processor(s) 102, or by otherprocessing devices within IHS 100. IHS 100 further includes one or moreinput/output (I/O) controllers 120, which support connection to, andprocessing of, signals from one or more connected input device(s) 122,such as a keyboard, mouse, touch screen, or microphone. I/O controllers120 also support connection to, and forwarding of, output signals to oneor more connected output device(s) 124, such as a monitor or displaydevice or audio speaker(s). In addition, IHS 100 includes universalserial bus (USB) 126 which is coupled to I/O controller 120.Additionally, in one or more embodiments, one or more deviceinterface(s) 128, such as an optical reader, a universal serial bus(USB), a card reader, Personal Computer Memory Card InternationalAssociation (PCMCIA) port, and/or a high-definition multimedia interface(HDMI), can be associated with IHS 100. Device interface(s) 128 can beutilized to enable data to be read from, or stored to, correspondingremovable storage device(s) 130, such as a compact disk (CD), digitalvideo disk (DVD), flash drive, or flash memory card. In one or moreembodiments, device interface(s) 128 can also provide an integrationpoint for connecting other device(s) to IHS 100. In one implementation,IHS 100 connects to remote IHS 140 using device interface(s) 128. Insuch implementation, device interface(s) 128 can further include GeneralPurpose I/O interfaces such as I²C, SMBus, and peripheral componentinterconnect (PCI) buses.

IHS 100 further comprises controller 135 (e.g., a server controller, aremote access controller such as an integrated DELL Remote AccessController (iDRAC), a Baseboard Management Controller (BMC), etc) whichincludes vACRM 138. The vACRM has the capability to support a vAC resetof IHS 100. IHS 100 also comprises a network interface device (NID) 132.NID 132 enables IHS 100 to communicate and/or interface with otherdevices, services, and components that are located external to IHS 100.These devices, services, and components can interface with IHS 100 viaan external network, such as example network 136, using one or morecommunication protocols. In particular, in one implementation, IHS 100uses NID 132 to connect to remote IHS 140 via an external network, suchas network 136. Remote IHS 140 is an example server or device from whicha vAC reset request can be issued to IHS 100.

Network 136 can be a wired local area network, a wireless wide areanetwork, wireless personal area network, wireless local area network,and the like, and the connection to and/or between network 136 and IHS100 can be wired or wireless or a combination thereof. For purposes ofdiscussion, network 136 is indicated as a single collective componentfor simplicity. However, it is appreciated that network 136 can compriseone or more direct connections to other devices as well as a morecomplex set of interconnections as can exist within a wide area network,such as the Internet.

FIG. 2 depicts a block diagram illustration of a data center environment(DCE) having a number of servers for which AC cycling can be performed,according to one or more embodiments. DCE 200 includes multiple servers,illustrated as servers 202 a-n, having respective antennas. DCE 200 alsoincludes remote site 214 and local terminal 218, each having an abilityto communicate with servers 202 a-n over a network via network switch212. Also illustrated in DCE 200 is smart phone 216, which has anantenna, enabling smart phone 216 to communicate with servers 202 a-n.Additionally, DCE 200 includes power distribution unit (PDU) 204, whichis implemented as an alternating current (AC) power strip that providesAC power via respective AC connection paths 206 a-n to servers 202 a-n.DCE 200 also includes network links 208 a-n that connect servers 202 a-nto network switch 212. PDU 204 is coupled to network switch 212 bynetwork communication path 210.

According to one aspect, a user requests a virtual AC cycle of at leastone server (e.g., server 202 a) via one of remote site 214, localterminal 218 and smart phone 216. As one example application, the usercan issue the request for the vAC cycle upon detecting that the serveris in an unresponsive operating state. The vACRM 114, operating withinservers 202 a-n, receives the vAC cycle request and in response toreceiving the request, sets a bit within a complex programmable logicdevice (CPLD) or other Auxiliary (AUX) based register to invoke a vACreset when a “Next System RESTART” command is issued. The vACRM 114 thenchanges a configurable vAC Recovery Policy to “Always Power ON on vACRestore” (i.e., turn on main rail power and initiate a server start-upprocedure when a restored vAC is detected). After changing the vACRecovery Policy, vACRM 114 uses a restart command to initiate a shutdownof server 202 a, which shutdown includes a shutdown of the main railpower, resulting in a removal of power from components of server 202 apowered by the main rail. Using auxiliary power switch 310 (FIG. 3),vACRM 114 removes AUX power from AUX powered components (i.e., switchesoff power to AUX powered components), based on the previously set bit.The vACRM 114 reapplies (i.e., switches on) AUX power to AUX poweredcomponents, following a preset interval. The vACRM 114 triggers a “DCpower-on” (i.e., a turning on of main rail power and initiation of theserver start-up procedure), in response to detecting a reapplied AUXpower, according to the vAC recovery policy.

A remote virtual AC cycle is issued to servers 202 a-n via a networklink (e.g., network link 208 a) that bypasses communication with a PDU(e.g., PDU 204). In other words, the remote vAC is performed without theneed for external, smart-switched PDUs and/or without requiring a humanin the datacenter to remove and reapply AC power manually. The remotevAC enables the server to power cycle the hardware, Main & AUX powerrails, emulating an AC power cycle, while incurring relatively lowcosts.

FIG. 3 is a block diagram illustration of an example server platformhaving an auxiliary power switch, according to one or more embodiments.IHS 300 includes power control sub-system (PCS) 302 and platformelectronic components (PECs) 330. PCS 302 includes chassis power supplyunit (PSU) 304 which provides main power illustrated as “V_12V” 306 fora main power rail and auxiliary power illustrated as “V_12V_AUX_ISO”308. In addition, PCS 302 includes first switch 310 (i.e., the auxiliarypower switch) which is coupled to PSU 304 at a PSU output port thatprovides “V_12V_AUX_ISO” 308. When configured in an ON state, firstswitch 310 yields “V_12VAUX” 312 at an output port of switch 310.“V_12VAUX” 312 represents an auxiliary power rail of IHS 300. PCS 302also includes system complex programmable logic device (CPLD) 314 andautonomous switch control 316 which is coupled to an output port ofsystem CPLD 314. Additionally, autonomous switch control 316 is coupledto switch 310. Also illustrated within PCS 302 is “vAC” cycle trigger318. In one embodiment, vAC cycle trigger 318 is provided by a hostapplication (e.g., application 112 of FIG. 1) based on a request that isreceived via an in-band management tool. However, in another embodiment,vAC cycle trigger 318 is provided by a server controller (e.g.,controller 135 of FIG. 1) based on a request that is received via anout-of-band management tool.

PECs 330 includes various types of components, including CPU 332. Inaddition, PECs 330 include second switch 336, third switch 344, fourthswitch 352 and fifth switch 356, which are respectively coupled tovarious electrical components and/or sub-systems. For example, secondswitch 336 is coupled to a number of components including CPLD 337, PCH338 and BMC 340. First CPLD switch control signal 342 is received bysecond switch 336 and is used to toggle between Main and Auxiliarypower. For example, second switch 336 utilizes Auxiliary power only whenMain power is not available. Third switch 344 is coupled to fan 346.Fourth switch 352 is coupled to Dual In-line Memory Module (DIMM) 354.Fifth switch not shown) is coupled to battery (not shown), whichprovides power to DIMM 354.

As illustrated, IHS 300 includes one or more switches (e.g., firstswitch 310). First switch 310 (i.e., auxiliary power switch)automatically connects chassis power supply auxiliary power (e.g.,“V_12V_AUX_ISO” 308) to server auxiliary power when AC power isavailable (e.g., “V_12VAUX” 312).

According to one or more aspects, virtual AC (vAC) trigger/request 318to the server (e.g., IHS 300) can be issued via an in-band connection toone of a host CPU/processor and a host OS. Alternatively, a vAC requestcan be issued via an out-of-band connection through a use of userapplications or via wireless fidelity (WiFi) technologies. A user canissue a vAC cycle request from a host/OS interface via standard in-bandtools. In one embodiment, these in-band tools can include a new vACreset option in a utility menu. Alternatively, these in-band tools caninclude a custom management application with an option to trigger a vACrequest.

When a server controller (135) (e.g., a BMC) is fully functional, orfunctional enough to deliver a vAC request via an out-of-bandconnection, an administrator/user/proprietary tool can issue a vACrequest targeting the system via standard OOB tools (e.g., RACADM, Webservices for Management (WSMAN), Redfish, etc). Issuing a vAC cycle to aserver (e.g., IHS 300) involves two steps: (a) shutting down the serverand removing AUX power to turn off power to all of the system logic(i.e., Main and AUX components/logic); and (b) ensuring that the server(e.g., IHS 300) can successfully power-up when AUX power is re-appliedas part of re-powering up the server.

According to one or more aspects, turning off all the power to systemlogic (i.e., Main and AUX components/logic) involves the followingenumerated steps: (1) A newly defined bit “vAC power cycle request bit”in CPLD 314 (or in another AUX based register(s)) is set, where the bitholds/registers a user request to toggle chassis AUX power on “next”system restart. According to one embodiment, application 112 is capableof directly setting the vAC power cycle request bit (i.e., withoutinvoking the BIOS), in response to receiving a power cycle request; (2)The “After_G3” (i.e., system OFF State where no power is consumed)policy setting in the platform controller hub (PCH)/Southbridge (e.g.,the “vAC Restart/Recovery policy” in the chipset), which is set to“Always Power up on new vAC application”, is changed. In oneimplementation, the vAC restart policy setting is located in a real timeclock (RTC) well of a corresponding chipset, and, as a result, ispreserved across vAC restart or vAC removal/loss operations (i.e., vACreset operations); (3) The previously described steps involved inturning off all the power to system logic can be optionally combined inone request via application to the platform using a Basic Input/OutputSystem (BIOS) System Management Interrupt (SMI) as themechanism/abstraction layer. In particular, the host application 112 orserver controller 135 can invoke the BIOS via SMI to (i) write to theCPLD (314) to set the “vAC power cycle request bit” and (ii) change thevAC restart policy in the chipset. In another implementation, theapplication can invoke the BIOS using a different mechanism, interface,or application programmable interface (API); (4) A “system restart”using one of a graceful shutdown and an ungraceful shutdown is issued.The “system restart” involves executing a “Direct current (DC) powercycle” of the system. The “DC power cycle” refers to a turning off andsubsequent returning of main system power accompanied by a respectiveshutdown and a respective start-up of the IHS. A graceful shutdowninvolves a command to “power off the system” which is proceeded by arequest to the host OS 108 to perform an established OS shutdownprocess. As a result, the graceful shutdown enables all work-in-progressto be saved and ensures data integrity. Unlike the graceful shutdown, anungraceful shutdown involves the command to “power off the system” butdoes not involve the established OS shutdown process; (5) Any of theabove four steps associated with turning off all the power to systemlogic can either be issued via an in-band path (e.g., OS 108/hostapplications 112) or via an out-of-band path (e.g., server controller135/BMC); (6) The system main rail power shuts off first (i.e., poweroff “S5” state) as part of system shutdown portion of a system powercycle; (7) The CPLD (e.g., CPLD 314), which runs off of the AUX powerrail, then issues a toggle-trigger to “AUX Power Control Switch” inresponse to the system being in the power off “S5” state. The CPLD mayoptionally reset the “vAC power cycle request bit” in the CPLD beforeissuing the vAC toggle-trigger to the AUX power control switch.Alternatively, the BIOS can be configured to perform this task (i.e., ofresetting the “vAC power cycle request bit” in the CPLD before issuingthe vAC toggle-trigger) on each system power up; and (8) The AUX powercontrol switch is an analog switch designed to toggle the AUX power tothe output side. For example, AUX power control switch 310 removes theAUX power from the switch's output side and then re-applies AUX powerafter a pre-determined short duration. At this step of powering off ofthe server when AUX power is removed from the switch's output side, allof the system components, except the power supplies (e.g., PSU 304), arein a powered off state.

Turning the server back ON (i.e., to complete the vAC cycle) andrestoring power to system logic (i.e., Main and AUX components/logic)involves the following number of enumerated steps. (1) AUX power controlswitch 310 is designed to re-apply AUX power to the switch's outputafter a fixed/predetermined duration, thereby initiating AUX powerapplication to CPLD 314, PCH 338 and all of the system components on theAUX power rail. (2) PCH 338/Chipset, which was previously set to “AlwaysPower up on vAC application”, on detecting vAC power restoration, willissue a system power ON sequence to power on the rest of the serversystem. (3) The system will power-up following the standard designedpower-sequencing of various rails and sub-systems. All AUX-poweredsubsystems are full restarted. (4) The BIOS re-programs/initializes thePCH to a user-configured setting for the vAC recovery option (i.e., aBIOS setup setting).

The steps involving removing and restoring power to system logic inorder to provide a remote vAC cycle of all of the server components areperformed without requiring an external smart-switched PDU and withoutrequiring manual AC cord removal and reinsertion by a data centertechnician.

In one or more alternate embodiments, a new one-shot BIOS attribute of“vAC restart on next boot=Enabled/disabled” can be created. When theattribute is set (i.e., enabled), the BIOS handles writing of respectivebits to CPLD and PCH registers to enable the same flow of steps whichresult in a vAC cycling of server components as described above.

In one or more related embodiments, a new option involves enhancementsto Advanced Configuration and Power Interface (ACPI) sleep states whichare reported to OS 108. This new option can enable an OS restart menu toinvoke a vAC restart based on a reported ACPI sleep state and/orstandard sleep states supported by OS 108, as per BIOS directive.

According to one or more aspects, added/modified functionality used tosupport the vAC process such as an addition of the new one-shot BIOSattribute and/or the enhancements to ACPI sleep states may be providedusing one or more firmware (FW) updates of criticalupdateable/programmable components in the AUX domain/rail.

As described above, a remote vAC cycle for all of the server componentscan be invoked/triggered via an in-band/host CPU interface or viaout-of-band/BMC interfaces. In addition, a selected reset/restart ofindividual components (e.g., the iDRAC, CPLD, etc) can be performedwithout restarting all of the server components.

According to one or more embodiments, a chipset watchdog timer (WDT)functionality and/or a BMC WDT timer functionality are expanded toinvoke full system vAC restart under specific conditions and based onplatform policy.

According to one or more aspects, the vAC is performed tore-initialize/clear server liquid crystal display (LCD) and similarcomponents as part of a full recovery of a server state from criticalfailures such as CPU IERR (i.e., internal error).

FIGS. 4 and 5 present flowcharts illustrating example methods by whichIHS 300, and specifically vAC cycle module 114/138 presented within thepreceding figures, perform different aspects of the processes thatenable one or more embodiments of the disclosure. Method 400 representsa method for performing a virtual AC reset via an in-band managementconnection. Method 500 represents a method for performing a virtual ACreset via an out-of-band management connection. The description of eachmethod is provided with general reference to the specific componentsillustrated within the preceding figures. It is appreciated that certainaspects of the described methods may be implemented via other processingdevices and/or execution of other code/firmware. In the discussion ofFIGS. 4 and 5, reference is also made to elements described in FIGS.1-3.

Method 400 begins at the start block and proceeds to block 402 at whichvACRM 114/138 receives a request via an in-band management tool for areset of vAC power being applied to IHS. vACRM 114/138 sets, using ahost application, a programmable bit to invoke virtual AC reset on anext system restart (block 404). Using the host application, vACRM114/138 changes a “vAC Recovery” policy to “Always Power ON on vACRestore” (block 406). vACRM 114/138 initiates a system restart viaOS/App mechanisms (block 408). vACRM 114/138 triggers and detects powerbeing removed from main rail powered components to provide the DC-offState (block 410). vACRM 114/138 removes AUX power from AUX poweredcomponents, based on the previously set programmable bit (block 412).Following a preset interval, vACRM 114/138 reapplies AUX power to AUXpowered components (block 414). vACRM 114/138 triggers “DC power-on” inresponse to detecting reapplied AUX power, according to “vAC recovery”policy (block 416). The process concludes at the end block.

Method 500 begins at the start block and proceeds to block 502 at whichvACRM 114/138 receives an administrator request via an out-of-bandmanagement tool for a reset of vAC power being applied to IHS. vACRM114/138 sets, using server controller 135, a programmable bit to invokevirtual AC reset on a next system restart (block 504). Using servercontroller 135, vACRM 114/138 changes a “vAC Recovery” policy to “AlwaysPower ON on vAC Restore” (block 506). vACRM 114/138 initiates a systemshutdown via server controller 135 (block 508). vACRM 114/138 triggersand detects power being removed from main rail powered components toprovide the DC-off State (block 510). vACRM 114/138 removes AUX powerfrom AUX powered components, based on the previously set programmablebit (block 512). Following a preset interval, vACRM 114/138 reappliesAUX power to AUX powered components (block 514). vACRM 114/138 triggers“DC power-on” in response to detecting reapplied AUX power, according to“vAC recovery” policy (block 516). The process concludes at the endblock.

In the above described flow charts, one or more of the methods may beembodied in a computer readable device containing computer readable codesuch that a series of functional processes are performed when thecomputer readable code is executed on a computing device. In someimplementations, certain steps of the methods are combined, performedsimultaneously or in a different order, or perhaps omitted, withoutdeviating from the scope of the disclosure. Thus, while the methodblocks are described and illustrated in a particular sequence, use of aspecific sequence of functional processes represented by the blocks isnot meant to imply any limitations on the disclosure. Changes may bemade with regards to the sequence of processes without departing fromthe scope of the present disclosure. Use of a particular sequence istherefore, not to be taken in a limiting sense, and the scope of thepresent disclosure is defined only by the appended claims.

Aspects of the present disclosure are described above with reference toflowchart illustrations and/or block diagrams of methods, apparatus(systems) and computer program products according to embodiments of thedisclosure. It will be understood that each block of the flowchartillustrations and/or block diagrams, and combinations of blocks in theflowchart illustrations and/or block diagrams, can be implemented bycomputer program instructions. Computer program code for carrying outoperations for aspects of the present disclosure may be written in anycombination of one or more programming languages, including an objectoriented programming language, without limitation. These computerprogram instructions may be provided to a processor of a general purposecomputer, special purpose computer such as a service processor, or otherprogrammable data processing apparatus to produce a machine, such thatthe instructions, which execute via the processor of the computer orother programmable data processing apparatus, performs the method forimplementing the functions/acts specified in the flowchart and/or blockdiagram block or blocks.

As will be further appreciated, the processes in embodiments of thepresent disclosure may be implemented using any combination of software,firmware or hardware. Accordingly, aspects of the present disclosure maytake the form of an entirely hardware embodiment or an embodimentcombining software (including firmware, resident software, micro-code,etc.) and hardware aspects that may all generally be referred to hereinas a “circuit,” “module,” or “system.” Furthermore, aspects of thepresent disclosure may take the form of a computer program productembodied in one or more computer readable storage device(s) havingcomputer readable program code embodied thereon. Any combination of oneor more computer readable storage device(s) may be utilized. Thecomputer readable storage device may be, for example, but not limitedto, an electronic, magnetic, optical, electromagnetic, infrared, orsemiconductor system, apparatus, or device, or any suitable combinationof the foregoing. More specific examples (a non-exhaustive list) of thecomputer readable storage device would include the following: anelectrical connection having one or more wires, a portable computerdiskette, a hard disk, a random access memory (RAM), a read-only memory(ROM), an erasable programmable read-only memory (EPROM or Flashmemory), an optical fiber, a portable compact disc read-only memory(CD-ROM), an optical storage device, a magnetic storage device, or anysuitable combination of the foregoing. In the context of this document,a computer readable storage device may be any tangible medium that cancontain, or store a program for use by or in connection with aninstruction execution system, apparatus, or device.

While the disclosure has been described with reference to exemplaryembodiments, it will be understood by those skilled in the art thatvarious changes may be made and equivalents may be substituted forelements thereof without departing from the scope of the disclosure. Inaddition, many modifications may be made to adapt a particular system,device or component thereof to the teachings of the disclosure withoutdeparting from the essential scope thereof. Therefore, it is intendedthat the disclosure not be limited to the particular embodimentsdisclosed for carrying out this disclosure, but that the disclosure willinclude all embodiments falling within the scope of the appended claims.Moreover, the use of the terms first, second, etc. do not denote anyorder or importance, but rather the terms first, second, etc. are usedto distinguish one element from another.

The terminology used herein is for the purpose of describing particularembodiments only and is not intended to be limiting of the disclosure.As used herein, the singular forms “a”, “an” and “the” are intended toinclude the plural forms as well, unless the context clearly indicatesotherwise. It will be further understood that the terms “comprises”and/or “comprising,” when used in this specification, specify thepresence of stated features, integers, steps, operations, elements,and/or components, but do not preclude the presence or addition of oneor more other features, integers, steps, operations, elements,components, and/or groups thereof.

The description of the present disclosure has been presented forpurposes of illustration and description, but is not intended to beexhaustive or limited to the disclosure in the form disclosed. Manymodifications and variations will be apparent to those of ordinary skillin the art without departing from the scope of the disclosure. Thedescribed embodiments were chosen and described in order to best explainthe principles of the disclosure and the practical application, and toenable others of ordinary skill in the art to understand the disclosurefor various embodiments with various modifications as are suited to theparticular use contemplated.

What is claimed is:
 1. An information handling system (IHS) comprising:a main power rail; an auxiliary (AUX) power rail; an auxiliary (AUX)power control switch coupled between a chassis power supply AUX powerand the AUX power rail; electronic components coupled to the AUX powerrail; a reset management module (RMM); a processor which executes theRMM and which is communicatively coupled to the AUX power controlswitch, wherein the processor: receives, by a controller at a host/OSinterface via one of an in-band management tool and an out-of-bandmanagement tool, a request for a virtual alternating current (vAC) resetof the IHS; and in response to receiving the request for the vAC reset:sets, via an application, a bit within an AUX register of an AUX baseddevice to invoke the vAC reset if a system restart command is issued;and performs the virtual AC reset of the system by using the AUX powercontrol switch to control a switching of AUX power to the AUX power railwhich is coupled to an output of the AUX power control switch, whereinthe processor: configures a vAC recovery policy to enable main railpower to be turned on and a system start-up procedure to be initiatedwhen a restored vAC is detected; executes at least one of (i) a write tothe AUX register to set said bit and (ii) a change of the vAC recoverypolicy setting to trigger a system re-start whenever vAC power isreapplied to said output, wherein said vAC recovery policy setting ismaintained within a controller circuitry of a core logic chipset and ispreserved across vAC reset operations; initiates said main rail powershut-down using a system restart command; and in response to detectingsaid main rail power shut-down while said bit is set, toggles thechassis AUX power to remove said power from the output of the AUX powercontrol switch; wherein the controller (i) sets said bit and (ii)changes the vAC recovery policy setting by performing one of (a)invoking the BIOS and (b) directly changing the vAC recovery policysetting.
 2. The IHS of claim 1, wherein to perform the switching, theprocessor: in response to receiving the request, executes a main railpower shut-down which switches off power to components powered by themain rail; in response to the main rail power being shut-down, switchesoff power from the output of the AUX power control switch and to AUXpowered electrical components; switches on power to the output of theAUX power control switch following a pre-established time interval afterswitching off power from the output of the AUX power control switch; andin response to switching on the power to the output of the AUX powercontrol switch, switches on main rail power and initiates a systemstart-up procedure.
 3. The IHS of claim 2, wherein the processor: resetssaid bit within said AUX register during one of (a) a period preceding aswitching off of power from the output of the AUX power control switchand (b) each system power-up period that follows a switching off ofpower from the output of the AUX power control switch.
 4. The IHS ofclaim 1, wherein: said reset is initiated in response to and to correcta fault resulting from an observed low level of responsivenessassociated with at least one of system hardware and system firmware. 5.The IHS of claim 1, wherein: said shutdown of the IHS comprises one of(i) a graceful shutdown of the IHS, wherein an established operatingsystem based shutdown procedure is executed and (ii) an ungracefulshutdown of the IHS, wherein the established operating system basedshutdown procedure is not executed.
 6. The IHS of claim 1, wherein: saidvAC reset is used to cycle the AUX power rail and is performed withoututilizing an external PDU switching and without requiring physicalremoval or physical re-applying of AC power of chassis power supplies,wherein said chassis power supplies remain within an active stateallowing stored bit information in the AUX based register to be used totrigger a restart of main power and a corresponding start-up of the IHS.7. The IHS of claim 1, wherein: the RMM is stored and executed within achassis power supply unit that provides the main power rail and the AUXpower rail.
 8. In an information handling system (IHS), aprocessor-implemented method comprising: receiving, at a host/OSinterface via an in-band management tool, a request for a virtualalternating current (AC) reset of the IHS; and in response to receivingthe request: setting, via an application, a bit within an AUX registerof an AUX based device to invoke the vAC reset if a system restartcommand is issued and changing a vAC recovery policy setting; andperforming the virtual AC reset of the system by using an auxiliary(AUX) power control switch to control a switching of an AUX power to anAUX power rail which is coupled to an output of the AUX power controlswitch, wherein the AUX power control switch is coupled between an AUXpower output of a chassis power supply and the AUX power rail, whereinthe performing includes: configuring the vAC recovery policy to enablemain rail power to be turned on and a system start-up procedure to beinitiated when a restored vAC is detected; executing at least one of (i)a write to the AUX based register to set said bit and (ii) a change ofthe vAC recovery policy setting to trigger a system restart whenever vACpower is re-applied to said output, wherein said vAC recovery policysetting is maintained within a controller circuitry of a core logicchipset and is preserved across vAC reset operations; initiating saidmain rail power shut-down using a system restart command; and inresponse to detecting said main rail power shut-down while said bit isset, toggling the chassis AUX power to remove said power from the outputof the AUX power control switch.
 9. The method of claim 8, furthercomprising: in response to receiving the request, executing a main railpower shut-down which switches off power to components powered by themain rail; in response to the main rail power being shut-down, switchingoff power from the output of the AUX power control switch and to AUXpowered electrical components; switching on power to the output of theAUX power control switch following a pre-established time interval afterswitching off power from the output of the AUX power control switch; andin response to switching on the power to the output of the AUX powercontrol switch, switching on main rail power and initiating a systemstart-up procedure.
 10. The method of claim 9, further comprising:resetting said bit within said AUX based register during one of (a) aperiod preceding a switching off of power from the output of the AUXpower control switch and (b) each system power-up period that follows aswitching off of power from the output of the AUX power control switch.11. In an information handling system (IHS), a processor-implementedmethod comprising: receiving a request to trigger a virtual alternatingcurrent (AC) reset of the IHS at a server controller via an out-of-bandmanagement tool; in response to receiving the request: setting, via theserver controller a bit within an AUX register of an AUX based device toinvoke the vAC reset if a system restart command is issued; and changinga vAC recovery policy setting by performing one of (a) invoking a BIOSand (b) directly changing the vAC recovery policy setting; andperforming the virtual AC reset of the system by using an auxiliary(AUX) power control switch to control a switching of AUX power to an AUXpower rail which is coupled to an output of the AUX power controlswitch, wherein the AUX power control switch is coupled between an AUXpower output of a chassis power supply and an AUX power rail, whereinthe performing includes: configuring a vAC recovery policy to enablemain rail power to be turned on and a system start-up procedure to beinitiated when a restored vAC is detected; executing at least one of (i)a write to the AUX based register to set said bit and (ii) a change ofthe vAC recovery policy setting to trigger a system re-start whenevervAC power is re-applied to said output, wherein said vAC recovery policysetting is maintained within a controller circuitry of a core logicchipset and is preserved across vAC reset operations; initiating saidmain rail power shut-down using a system restart command; and inresponse to detecting said main rail power shut-down while said bit isset, toggling the chassis AUX power to remove said power from the outputof the AUX power control switch.
 12. The method of claim 8, wherein:said reset is initiated in response to, and in order to correct, a faultresulting from an observed low level of responsiveness associated withat least one of system hardware and system firmware.
 13. The method ofclaim 8, wherein: said shutdown of the IHS comprises one of (i) agraceful shutdown of the IHS, wherein an established operating systembased shutdown procedure is executed and (ii) an ungraceful shutdown ofthe IHS, wherein the established operating system based shutdownprocedure is not executed.
 14. The method of claim 8, wherein: said vACreset is used to cycle the AUX power rail and is performed withoututilizing an external PDU switching and without requiring physicalremoval or physical re-applying of AC power of chassis power supplies,wherein said chassis power supplies remain within an active stateallowing stored bit information in the AUX based register to be used totrigger a restart of main power and a corresponding start-up of the IHS.